VLSI Design 

Unit wise Important Questions

UNIT-I

1. Explain the nMOS enhancement mode fabrication process for different conditions of Vds.

2. Derive an expression for transconductance of an n-channel enhancement MOSFET

    operating in active region.

3. Explain in detail the p-well process for CMOS fabrication indicating the masks used.

4. Compare the relative merits of three different forms of pull-up for an inverter circuit.

    What is the best choice for realization in nMOS and CMOS technology?

5. Compare BiCMOS technology with other Technologies.

6. What are the additional two layers in BiCMOS technology compared to others?

    With neat sketches explain BiCMOS fabrication process.

7.  Show that the switching speed of an enhancement MOSFET varies inversely as

     the square of the channel length.

8. Derive an equation for Ids of an n-channel Enhancement MOSFET operating in

    Saturation region.

9. An nMOS transistor is operating in saturation region with the following

    parameters. VGS = 5V; Vtn = 1.2V; W/L = 110; μnCox = 110 μA/V2. Find

    transconductance of the device.

UNIT-II

1. Draw a stick diagram and layout for two input CMOS NAND gate indicating all the

    regions and layers.

2. Explain 2 μm Double Metal, Double Poly CMOS / BiCMOS Rules.

3. What are the λ-based design rules? Give them for each layer.

4. Draw a stick diagram for CMOS logic Y= (A+B+C)Ꞌ.

5. Explain with suitable examples how to design the layout of a Gate to maximize

    Performance and minimize area.

6. Design a stick diagram for two input pMOS NAND and NOR gates.

7. Explain about double poly CMOS rules

UNIT-III

1. Explain the issues involved in driving large capacitor loads in VLSI circuit regions.

2. Calculate the gate capacitance value of 5 mm technology minimum size transistor with

    gate to channel value is 4 x 10-4 pF/mm2.

3. What is inverter delay? How delay is calculated for multiple stages? Explain.

4. Two nMOS inverters are cascaded to drive a capacitive load CL=16Cg. Calculate pair

    delay Vin to Vout in terms of τ.

5. How does depletion regions around source and drain are affected due to scaling

    down of device dimensions? Explain.

6. Derive the expression for propagation delay in the case of cascaded pass transistors.

7. Describe the following briefly

    (i) Cascaded inverters as drivers (ii) Super buffers (iii) BiCMOS drivers.

8. Design a layout diagram for CMOS 3-input NAND gate.